`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: WuHan University
// Engineer: Leequo94
// 
// Create Date: 2018/09/13 
// Design Name: 
// Module Name: shift_fifo2line
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// input sequence: 
// s_axis_tvald : ______|``````````.........``````````|________
// s_axis_tdata : ______|XXXXXXXXXX.........XXXXXXXXXX|________
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module shift_fifo2line # 
( 
    parameter   COL = 1920,
    parameter   ROW = 1080
)
(
    input       wire            clk,
    input       wire            rst_n,
    input       wire            s_axis_tvald,
    input       wire    [7:0]   s_axis_tdata,
    output      wire            m_axis_tvald,
    output      wire    [7:0]   m_axis_tdata0,
    output      wire    [7:0]   m_axis_tdata1
);

wire rst = !rst_n;
wire wr_clk = clk;
wire wr_en = s_axis_tvald;
wire [7:0] din = s_axis_tdata;
wire rd_clk = clk;
reg rd_en;
wire [7:0] dout;
wire [10:0] rd_data_count;
////////////////////////////////////////////////////////////////////////////////
fifo_8x2048 fifo_8x2048_inst (
  .rst          (rst            ),          // input wire rst
  .wr_clk       (wr_clk         ),          // input wire wr_clk
  .wr_en        (wr_en          ),          // input wire wr_en
  .din          (din            ),          // input wire [7 : 0] din
  .full         (               ),          // output wire full
  .wr_data_count(               ),          // output wire [10 : 0] wr_data_count
  
  .rd_clk       (rd_clk         ),          // input wire rd_clk
  .rd_en        (rd_en          ),          // input wire rd_en
  .dout         (dout           ),          // output wire [7 : 0] dout
  .empty        (               ),          // output wire empty
  .rd_data_count(rd_data_count  )           // output wire [10 : 0] rd_data_count
); 
////////////////////////////////////////////////////////////////////////////////
reg s_axis_tvald_d1;
always @ (posedge clk,negedge rst_n)
begin 
    if (!rst_n) begin 
        s_axis_tvald_d1 <= 1'd0;
    end 
    else begin 
        s_axis_tvald_d1 <= s_axis_tvald;
    end 
end 
////////////////////////////////////////////////////////////////////////////////
reg [15:0] row_cnt;
always @ (posedge clk,negedge rst_n)
begin 
    if (!rst_n) begin 
        row_cnt <= 16'd0;
    end 
    else if (s_axis_tvald_d1 & !s_axis_tvald) begin 
        if (row_cnt == ROW) begin 
            row_cnt <= 16'd0;
        end 
        else begin 
            row_cnt <= row_cnt + 1'd1;
        end 
    end 
    else begin 
        row_cnt <= row_cnt;
    end 
end 
////////////////////////////////////////////////////////////////////////////////
always @ (posedge clk,negedge rst_n) 
begin 
    if (!rst_n) begin 
        rd_en <= 1'd0;
    end 
    else if (row_cnt >= 16'd1 && row_cnt <= ROW) begin 
        rd_en <= s_axis_tvald;
    end 
    else begin 
        rd_en <= 1'd0;
    end 
end 

reg m_axis_tvald_reg;
always @ (posedge clk,negedge rst_n) 
begin 
    if (!rst_n) begin 
        m_axis_tvald_reg <= 1'd0;
    end 
    else begin 
        m_axis_tvald_reg <= rd_en;
    end 
end 
////////////////////////////////////////////////////////////////////////////////
reg [7:0]dat1;
reg [7:0]dat2;
always @ (posedge clk,negedge rst_n)
begin 
    if (!rst_n) begin 
        dat1 <= 8'd0;
        dat2 <= 8'd0;
    end 
    else begin 
        dat1 <= s_axis_tdata;
        dat2 <= dat1;
    end 
end 
assign m_axis_tvald = m_axis_tvald_reg;
assign m_axis_tdata1 = dat2;
assign m_axis_tdata0 = dout;
////////////////////////////////////////////////////////////////////////////////

endmodule 
